1. Field of the Invention
The present invention relates to reliability and packaging electronic of devices, particularly integrated circuit devices. More particularly, the present invention relates to a methodology for verifying the reliability of the interface between bond pads and other structures in integrated circuits. The present invention further achieves efficient use of chip area by providing that at least a portion of each electrostatic discharge (ESD) device is positioned under a bond pad, improving device density.
2. Discussion of the Related Art
Integrated circuit devices are typically packaged. One of the principal functions of the package is to allow connection of the chip to a circuit board or other electronic product. Such connection can generally not be made directly from the chip to the target product due to the thin, fragile microscopic metal e us ed to interconnect the several components on the chip surface. Many metal leads are typically about 0.6 xcexc m thick and less than 1.0 xcexc m wide. Indeed, many of the surface features of current production integrated circuits are xe2x80x9csubmicronxe2x80x9d or less than 1.0 xcexc m in width.
The wire currently available is typically in the range of 17 to 30 xcexc m in diameter, many times larger than the integrated circuit""s surface wiring. This difference in the size of these two wing structures is one of the reasons that Chip source wiring usually terminates at bond pads disposed on the chip, typically arrayed about the periphery of the chip as a pitch transformer. Traditionally of course, bond pads have been restricted to the chip periphery to avoid wire crossings. After the chip including the bond pads is formed, fine wiring in the form of bond or lead wire typically connects the bond pads to the substantial lead system (a.k.a. lead flame) that connects the package chip to the device in which is installed. One common bond pad material is aluminum, deposited dug chip fabrication. Bond wires are often gold or aluminum and are typically connected to the bond pads by means of metal balls or wedge bonds formed at the end of the bond wires and applied to the bond pad. Bond wires may be attached by thermosonic bonding, or other wire attachment methodology well known to those of ordinary skill in the art.
The first problem, which occurs in some integrated circuit devices, is cratering in the layers under the bond pads, generally fracture of the silicon and dielectric oxide layers. This phenomenon is sometimes referred to as xe2x80x9cbond pad crateringxe2x80x9d. While studies to determine exact meachanisms for crater initiation and propagation are still underway, an overview of some of the known mechanics of crater formation is discussed as follows.
One process, which has been shown to be cotributory to crater initiation, is the use of thermosonic attachment methodology for attaching bond wires to bond pads. Thermosonic bonding employs ultrasonic vibration, typically about 60-120 kHz, to form the bond. This dynamic is shown in FIG. 1. Having reference to that Figure, there is shown a cross-section through an integrated circuit (IC) device 1, the device formed of a plurality of layers and including at least one bond pad 2. In this example, the layers of the device 1 include silicon substrate 4, field oxide layer 6, BPSG layer 8, passivation layer 9, and plastic encapsulant 10. A wire bond is shown at 12, including ball 14. Noted in this Figure, the center of the die is located toward the direction labeled xe2x80x9cZxe2x80x9d. This listing of layers in the device is not meant to be exhaustive, but is rather illustrative of some of the several layers of a micro-electronic device known in the art.
During the wire bonding process, wire bond ball 14 is attached to bond pad 2 utilizing, for example, thermosonic bonding. The bonding process can induce microcracks, for example as shown at 20. With repeated thermal cycling, these microcracks can propagate, for instance as shown at 24, in the layers beneath the bond pad, causing chip failure. Some of these mechanisms are described below.
FIGS. 2A, 2B, and 2C are plan views of a section of a microdevice directly beneath a bond pad, following chemical removal of the bond wire ball, and demonstrating microcrack initiation and propagation. FIGS. 2Axe2x80x2, 2Bxe2x80x2, and 2C xe2x80x2 are cross-sections through the same section, however with the bond pads and bond wires intact.
Having reference now to FIG. 2, the physical propagation of a microcrack into a full-blown pad crater is shown. At FIGS. 2A and 2Axe2x80x2 a microcrack 20 has been formed in a layer immediately beneath bond at 2. With repeated the thermal cycling, this microcrack propagates in the direction shown at 26 in FIGS. 2B and 2Bxe2x80x2. With continued thermal cycling, crack propagation moves in a generally elliptical manner (FIG. 2B), and downward (FIG. 2Bxe2x80x2). It should be noted that this elliptical crater (FIG. 2Bxe2x80x2) is formed with its short axis aligned along a line originating substantially near the chip center.
At FIG. 3 is shown a scanning electron microscope (SEM) image of two areas underlying bond pads of a device 1, which failed due to bond pad cratering. This generally elliptical crater formation, and its alignment with the center of the device, as previously discussed, is clearly shown in these photomicrographs. Cratering induces a subtle and insidious reliability problem which integrated circuit devices: the craters so formed generally preclude reliable electrical contact between the chip""s surface wiring and the bond pads, and hence with any device to which the package integrated circuit is electrically connected.
Moreover, this contact failure is often intermittent, rendering the chip unreliable and the defect difficult to detect.
Finally, the formation of craters is a progressive process. This means that while a pre-disposition for crater formation, in the form of the previously discussed microcracks, and attendant chip failure may be present when the chip is going through the chip test procedures during manufacturing the crater may not yet actually have formed This pre-disposition is referred to herein as xe2x80x9ccrater jeopardyxe2x80x9d. It is only after a substantial number of thermal cycles that the crater forms, and attendant chip failure occurs.
It will be understood by those having skill in the art that the bond pad cratering phenomena previously ed are still under investigation. While it is generally believed that microcracks are initiated by stresses induced by the dynamic force of the gold ball at touch-down impact, the static force applied after touch-down, the level of ultrasonic energy, mechanical vibrations before or after bonding, and/or the hardness of the gold ball and the pad, the role which each of these mechanisms plays in crack/crater formation is still under investigation. Moreover, while the formation of cracks is believed to be dependent on the bonding mechanism, bond parameters, the thickness of the wire bond pad, and characteristics of the wire bond material being bonded, the roles of each of these mechanisms is also under investigation. Furthermore, continued research has shown that thermal cycling and shock during the plastic encapsulation process may play a role in propagating bond pad crater formation.
While a number of mechanisms and procedures are currently being investigated to prevent bond pad crater formation and attendant chip failure, given the insidious nature of the onset of crater formation, what is especially important is a practical methodology to detect microcracks under the bond pads during the manufacturing process. The methodologies previously utilized to detect bond pad crack/crater formation are insufficient as being laborious and destructive as will now be described
A first prior art methodology for monitoring crater jeopardy is by destructive decapitation and deprocessing, including the chemical removal of the ball bonds, followed by visual inspection and high magnification. The results of one such SEM examination of the area under two bond pads sufferin from bond pad crater formation is shown in FIG. 3. It will be appreciated that while this monitoring for crater jeopardy is particularly effective, it is the both laborious and destructive, rendering the device inoperative and unfit for further service. Clearly, this destructive and labor-intensive process cannot be effective for shippable products.
The second prior art methodology has been to undertake one or more functional tests of the chip subsequent to encapsulation. As previously discussed, one of the factors known to be important in bond pad crater formation is thermal cycling. Accordingly, it will be appreciated that it may require hundreds or even thousands of device heat/cool cycles before microcracks develop into full-blown bond pad craters, with an attendant bond pad failure sufficient to trigger a functional test. Accordingly, this methodology has not proven particularly effective. Moreover, utilization of this test methodology has been shown to reduce the life expectancy of the device.
Finally, there exist special test structures for electrical detection of the problem. These usually include continuity tests, or test for electrical leakage by structures under the pad. While these test structures have in some cases been shown to be effective for the detection of larger cracks and bond pad craters, they are not the optimal solution to the problem. In the first place, the use of these test structures introduces one or more additional processes during manufacturing. Secondly, the accuracy and reliability of these test structures for detecting the microcracks shortly their inception has not been proven.
Another problem relates to the inclusion of on-chip electrostatic discharge (ESD) devices. Typically, an ESD device 40 is connected between a bond pad 42 and a device 44 to be protected (FIG. 4), the bond pad 42 being connected to pin 45. The ESD device 40 includes a diffused or deposited resistor 46 connected between the pad 42 and the device 44 to be protected, resistor 46 acting as a diode 48 connected to Vss, and a pair of large NMOS transistors 52, 54 connected to the conductor 51 between the resistor 46 and pad 42. In normal operation of the ESD device 40, transistors 52, 54 are connected to voltage source Vdd and voltage source Vss, and diode 48 is connected to voltage source Vss, as shown. Another, smaller NMOS transistor 56 is connected to the gates of transistors 52, 54 and to voltage source Vss. The NMOS field transistor 56 has its gate connected to voltage source Vdd. The transistors 52, 54, 56, resistor 46 and diode 48 are typically laid out on the chip beside the associated die pad 42.
It will be seen that in particular the two large transistors 52, 54 occupy a large amount of chip area. It will be understood that improvement in device density on the chip is continually being sought, in order to improve operating performance and manufacturing efficiency.
Therefore, what is needed is a method to detect the formation of microcracks in the substrate immediately below the bond pad or bond pads of a micro-device. The methodology should enable the testing of each device during the manufacturing process without resorting to destructive test techniques. Moreover, the methodology should be capable of being implemented without unduly complicating or lengthening the normal manufacturing process for such devices. The methodology should not require additional bond pads or pins in the semiconductor device.
What is further needed is a way to improve chip density, in particular by laying out the ESD device and bond pad in a manner which provides that the resulting structure occupies less chip area than previous designs.
An especially elegant solution to these problems would be a single solution capable of simultaneously addressing and solving these two disparate issues.
The present invention teaches a methodology whereby 100 percent of the pads on chips undergoing manufacture can be effectively tested for the formation of cracks, most importantly small cracks, beneath the wire bond pad The methodology is non-descriptive in nature, and does not overly complicate the manufacturing process. The methodology uses a portion of an electrostatic discharge (ESD) device associated with the pad in such testing, with at least a portion of the ESD device positioned under the pad so that chip area is used effectively.
The transistors of an ESD device are positioned generally side-by-side beneath a bond pad. A diagnostic voltage is applied to a transistor and current there through is measured by an ammeter. In the event that all gates of the transistor are intact, current will be measured, as determined by the intact state of the gates. The intact state of the gates indicates that little or no cracking/cratering has occurred in the device beneath this transistor. In the event that such cracking/cratering has occurred beneath the transistor, this will cause agate of the transistor to fracture, resulting in less current flowing through the transistor than if all gates were intact. This lower current can readily be noted by observation of the ammeter, indicating cracking/cratering beneath that area of the transistor. The other transistor beneath the bond pad is used in a like manner to test for cracks/craters there beneath.
By positioning a portion of the ESD device under a pad, a significant amount of chip area is saved, contributing significantly to chip density. Moreover, the testing step used to implement the methodology is not particularly time consuming, thereby aiding in economy of manufacture.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described embodiments of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.